Both Intel and AMD agree that, from a programmer's viewpoint:
Loads cannot be reordered relative to other loads.
Stores cannot be reordered relative to other stores.
Intel64 Architecture Memory Ordering White Paper
<http://developer.intel.com/products/processor/manuals/318147.pdf>
AMD64 Architecture Programmer's Manual, Volume 2: System Programming
<http://www.amd.com/us-en/assets/content_type/\
white_papers_and_tech_docs/24593.pdf>
Signed-off-by: Keir Fraser <keir.fraser@eu.citrix.com>
#define __HAVE_ARCH_CMPXCHG
+/*
+ * Both Intel and AMD agree that, from a programmer's viewpoint:
+ * Loads cannot be reordered relative to other loads.
+ * Stores cannot be reordered relative to other stores.
+ *
+ * Intel64 Architecture Memory Ordering White Paper
+ * <http://developer.intel.com/products/processor/manuals/318147.pdf>
+ *
+ * AMD64 Architecture Programmer's Manual, Volume 2: System Programming
+ * <http://www.amd.com/us-en/assets/content_type/\
+ * white_papers_and_tech_docs/24593.pdf>
+ */
+#define rmb() barrier()
+#define wmb() barrier()
+
#ifdef CONFIG_SMP
#define smp_mb() mb()
#define smp_rmb() rmb()
w = x;
}
-#define mb() asm volatile ( "lock; addl $0,0(%%esp)" : : : "memory" )
-#define rmb() asm volatile ( "lock; addl $0,0(%%esp)" : : : "memory" )
-#define wmb() asm volatile ( "" : : : "memory" )
+#define mb() \
+ asm volatile ( "lock; addl $0,0(%%esp)" : : : "memory" )
#define __save_flags(x) \
asm volatile ( "pushfl ; popl %0" : "=g" (x) : )
*p = v;
}
-#define mb() asm volatile ( "mfence" : : : "memory" )
-#define rmb() asm volatile ( "lfence" : : : "memory" )
-#define wmb() asm volatile ( "" : : : "memory" )
+#define mb() \
+ asm volatile ( "mfence" : : : "memory" )
#define __save_flags(x) \
asm volatile ( "pushfq ; popq %q0" : "=g" (x) : :"memory" )